(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of self aligned dual damascene structures are described which lower parasitic capacitance.
As a background to the current invention, the damascene processing is an alternative method for fabricating planar interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide RIE, then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
The damascene approach has been adopted in many applications, since it efficiently provides the high yield and large process windows required for volume manufacturing. The use of CMP leads to a decrease in the number of interlevel shorts and lowers defect densities, since unwanted surface material is easily removed. Upon completion of CMP, the wafer surface is returned in a globally planar state, extending process windows for subsequent process steps, i.e., lithographic, etching, and CMP processing steps.
Key to the damascene processing approach is that the deposited conductive metal is deposited into a previously deposited patterned insulator. This is desirable because mask alignment, dimensional control, rework, and the etching process are all easier when applied to a dielectric rather than metal films. Damascene processing achieves these benefits by shifting the enhanced filling and planarization requirements from dielectric to metal films, and by shifting control over interconnect thickness from metal deposition to insulator patterning and metal CMP.
Sputter deposition has some key advantages as a metal deposition technique because it can be used to deposit many conductive materials, at high deposition rates, with good uniformity and low cost of ownership. Conventional sputtering does not fill or coat recessed features well. Sputtered atoms are typically ejected from a target in all directions, though the degree of flux directionality depends on the specific material being deposited, and on deposition conditions. Conventional sputtering fill is poorer for deeper, narrower (high-aspect-ratio) features. In addition, fill is especially bad for corners of recesses, which have relatively small acceptance angles for flux, and for thick depositions, since the upper surface deposition can block incoming flux and produce a void in the recessed feature.
The fill factor by sputter deposition has been significantly improved by collimating the sputtered flux. A collimated flux is produced by removing sputtered flux that approaches the substrate at a large angle from the surface normal. Typically, this is achieved by inserting between the target and substrate a collimator plate having an array of hexagonal cells.
Collimated sputtering is acceptable for thin liner depositions to cover features having moderate aspect ratios, but is not an appropriate technique for the complete filling of such features. Instead, for short-distance wiring such as studs and bit lines for which the high conductivity of Al is not required, chemical-vapor-deposited (CVD) W has proven to be a robust process that integrates easily with liner deposition and CMP to provide a manufacturing interconnect module. In addition, the W is easily patterned using CMP since it is hard and corrosion-resistant. It is also compatible with RIE formation of overlying Al-based wires, since it offers excellent etch selectivity in the preferred Cl-based chemistries.
Chemical vapor deposition (CVD) of W usually requires an underlying conductive barrier and "seed" layers to prevent consumption of substrate Si from reaction with WF.sub.6 at the contact level, and to promote distributed nucleation and low contact resistance. A layer of Ti is used since it provides good adhesion and low contact resistance. However, the Ti alone is not sufficient, because the F from the WF.sub.6 reacts with the Ti and produces a brittle, high-resistivity compound. However, the use of a TiN film between the Ti and W solves these problems by enhancing W nucleation while preventing the reaction of F with the Ti or any exposed Si. A W seed layer is then formed on the TiN.
Since Ti-based liners are less conductive and less easily polished than W, it is desirable to keep the liners as thin as possible. However, since the sputtered (PVD) liners are not conformal, inadequate coverage of recesses or foreign material defects can allow F to react with the underlying Ti, causing the liners to detach from their substrate. The TiN layer can crack and curl up, since the film is in tension. The CVD W can then deposit on the rolled-up TiN and these formations are termed tungsten "mounds" or "mushrooms". Improvements in commercial process equipment have improved the CVD liners, for example, the CVD TiN and Ti processes. Furthermore, CVD Ti and TiN offer good conformality, but require higher deposition temperatures and contain higher levels of impurities than do the sputtered (PVD) films.
After deposition, CMP is applied to complete the inlaid structure. In the CMP process, material is removed from the wafer through the combined effects of a polish pad and an abrasive slurry. The chemical dissolution of material is aided by a mechanical component which is useful in removing passivating surface layers. Chemical and mechanical selectivity's between materials are desired, since CMP must remove the metal overburden without removing appreciable amounts of inlaid metal or reducing interconnect thickness.
Scratching of the polished surface must also be avoided. Scratches in the inlaid metal can reduce the cross section locally, resulting in an elevated current density and/or elevated stress, thereby accelerating interconnect failures.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes.
Alternatively, the wire recesses can be formed first, but this approach makes the photolithography for the studs more difficult, since the resulting surface is less planar. Next, the stud/wire metallization is deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
The dual-damascene process can be more difficult to fill and planarization than the single-damascene processing. Specifically, the metal films must now fill features having aspect ratios much greater than 1. This can be attained with CVD W, provided the adhesive liner covers the recessed surfaces. To obtain adequate liner coverage using collimated sputtered (PVD) Ti/TiN liners, a larger liner thickness must be applied, which is then difficult to polish away, without dishing (W dishing due to its easy removal by CMP). Furthermore, the conformal filling afforded by CVD W results in local recesses over the high-aspect-ratio dual-damascene features that contribute to dishing during polishing.
It is a general object of the present invention to provide a novel and improved method for using a self aligned dual damascene process for fabricating self aligned dual damascene structures which have low parasitic capacitance (lowering RC time constant).
(2) Description of Related Art
The present invention is a new and improved method for using a self aligned dual damascene process which produces special structures with low parasitic capacitance for quarter micron and below semiconductor devices. Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,814,557 entitled "Method of Forming an Interconnect Structure" granted Sep. 29, 1998 to Venkatraman et al describes a method for forming copper dual damascene structures. An interconnect structure is formed by filling a dual damascene structure with conductive material. A barrier layer is formed to serve as a seed layer and to prevent the out diffusion of copper. A first conductive layer is formed to fill a first portion of the damascene structure. A second conductive layer is then formed to complete the filling of a second portion of the damascene structure. A chemical mechanical polishing (CMP) process is then used to remove any excess conducting material.
U.S. Pat. No. 5,801,094 entitled "Dual Damascene Process" granted Sep. 1, 1998 to Yew et al. describes a dual damascene method of forming a two level metal interconnect structure by first providing an interlevel oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer, interlevel dielectric (ILD), is provided over the etch stop layer. A photoresist mask is then provided over the interlevel dielectric (ILD) with openings in the mask exposing portions of the ILD layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The ILD layer is etched and the etching process continues to form openings in the ILD layer where the ILD is exposed by openings in the etch stop layer. Therefore, with a single etch step, the openings for both the second level wiring lines and the first level interconnects are defined. The dual damascene process forms holes (vias and contacts) and wiring lines (interconnect lines) simultaneously. Metal is then deposited over the structures and excess metal is removed by chemical mechanical polishing (CMP) to define the two level wiring and interconnect structure.
U.S. Pat. No. 5,795,823 entitled "Self Aligned Via Dual Damascene" granted Aug. 18, 1998 to Avanzino et al describes a method of a self-aligned dual damascene process. A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as "self aligned mask" for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. The partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. The conductive line openings and vias are filled with the same conductive material.
U.S. Pat. No. 5,753,967 entitled "Damascene Process for Reduced Feature Size" granted May 19, 1998 to Lin describes a method for a dual damascene process. Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening. An object of the invention is describes as an integrated semiconductor device containing an interconnection structure of planarized layers having minimal interwiring spacing. Also described is an improved damascene method for forming an interconnection structure having a conductive pattern wherein the conductive lines and/or interwiring spacing is less 0.35 microns. The objects are described as a semiconductor device comprising: a first dielectric layer, comprising a first dielectric material, having an upper surface, a lower surface, and a first opening extending through the first dielectric layer from the upper surface to the lower surface, wherein the first opening has a first dimension defined by a first sidewall having a finite thickness comprising a second dielectric material.
U.S. Pat. No. 5,635,423 entitled "Simplified Dual Damascene Process For Multi-Level Metallization and Interconnection Structure" granted Jun. 3, 1997 to Huang et al describes a method for a dual damascene processes. A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a "modified" dual damascene process. An opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer in between. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.
The present invention is directed to a novel and improved method of fabrication an integrated circuit, in which a self aligned dual damascene process and structure are formed, easing processing and lowering parasitic capacitance. The method of the present invention requires less processing time, has lower cost than conventional dual damascene methods and produces self aligned dual damascene interconnect line and vias structures with low parasitic capacitance.